1. Field
The present invention relates generally to improvements in time to digital conversion circuits and more particularly pertains to automatic calibration circuits for Vernier time to digital converters and improvements thereto.
2. Description of the Related Art
Time to digital conversion is often used in high speed electronic applications for determining the precise phase or timing of a signal utilized by the electronic application circuitry. A time to digital converter is a device or circuit that converts a pulsed signal into a digital representation of the timing of such pulses for circuits that require accurate timing of events. For example, all digital phase locked loops (ADPLL) commonly use a time to digital converter to ensure proper operation. An input signal is sampled via a reference clock at the outputs of a series of inverters or buffers that operate as a delay line along the propagation path of the input signal. This delay of the input signal translates into a phase quantization proportional to the delay and the operating frequency of the input signal. Thus, by decoding the samples of the input signal at the various delays, the phase of the input signal can be determined. A more accurate or precise phase quantization allows for increased accuracy in determining the phase.
Traditional time to digital converters can only quantize the phase component of an input signal roughly, lending to inaccuracies in the precise determination of the phase component of the input signal. In an effort to improve such conversion methods, Vernier time to digital converters have been employed. Similar to the traditional converters, Vernier time to digital conversion circuits utilize an additional delay line disposed along the propagation path of the reference clock for sampling the input signal. The delay line for the reference clock acts faster than the delay line for the input signal. Thus, in a Vernier time to digital converter, the input signal travels through a slower delay path and is sampled by a reference clock signal that travels through a faster delay path. By shifting the rising edge of the reference clock signal due to the faster delay path, improved phase quantization can be obtained compared to traditional time to digital converters. In Vernier circuits, the phase quantization is instead proportional to the difference in the delays between the two delay lines. Maintaining this designed difference in the delays of the two delays lines is critical to proper operation.
Conventional calibration of time to digital conversion circuits is typically performed via elaborate histogram data collecting followed by extensive analysis, often requiring off-board or off-line circuitry or systems. Such calibration is both expensive in time required for such data collection, manipulation and analysis and also in equipment and component manufacturing expense. Furthermore, in conventional calibration, the Vernier time to digital circuit may be difficult to calibrate once installed into or amongst other system circuitry due to the external connections and off-line analysis that is often required. Thus, a method or apparatus for accurately maintaining the ratio of the delays of the two delay lines is desired. The method or apparatus would desirably be capable of providing on-board Vernier time to digital calibration and require a minimum of assumed component operational parameters. The method or apparatus would desirably be capable of automatic calibration without extensive user analysis of data and would be capable of activation only when calibration is needed in order to reduce power consumption or other interference with connected circuits. Furthermore, the method or apparatus would desirably be of minimal increased cost or complexity to the Vernier time to digital conversion circuit.